This invention relates to a method and apparatus for forming a thin film on a substrate by using an electron beam.
In the past, to form a pattern on a semiconductor substrate, methods shown in FIGS. 1A through 1E and FIGS. 2A through 2D have been used. According to a method shown in FIGS. 1A to 1E, material 12 utilized to form a pattern is deposited on a semiconductor substrate 11 by vapor deposition or sputtering process (FIG. 1A). Then, as shown in FIG. 1B, a layer of a photoresist 13 is formed and exposed to light or an electron beam to be patterned as shown in FIG. 1C. Then, the film of the material 12 is etched by chemical etching or dry etching process by using the resist pattern 13 as a mask, as shown in FIG. 1D. Finally, the resist pattern 13 is removed to form a patterned film as shown in FIG. 1E.
FIGS. 2A through 2D show another method in the prior art using lift-off process. More particularly, a film of a resist 22 is first coated on a semiconductor substrate 21 as shown in FIG. 2A. Then, the resist film 22 is patterned as shown in FIG. 2B by exposing it to light or an electron beam. Then, a pattern material 23 is vapor deposited on the patterned resist film 22 and the substrate 21 as shown in FIG. 2C. After that, the patterned resist 22 is removed to leave pattern material 23 on the substrate 21 as shown in FIG. 2D.
The prior art methods are disadvantageous in that;
(1) the formation process is prolonged, and PA1 (2) the formation of a sufficiently fine pattern is impossible.
Among various semiconductor devices, a gallium arsenide (GaAs) device is expected to be highly integrated because of its high operation speed and high output.
To integrate GaAs elements, it is necessary to isolate elements from each other. Such element isolation has been made as follows. FIG. 6 is a cross-sectional view showing one example of the prior art device. As shown, an electroconductive N-type GaAs layer 220 is formed on the surface of a semi-insulator GaAs substrate 210 and then etched to form GaAs layer cell isolating regions 230 are formed. A source electrode 250, a gate electrode 260 and a drain electrode 270 are formed in each cell region 240. In this case, the inter-cell isolation is made by utilizing the fact that the resistance of the substrate is high. Although the resistivity of the substrate is made high by doping chromium in the GaAs substrate, there is a problem that the concentration of chromium in the surface of the substrate is decreased by the heat treatment at the time of forming the cells, thus decreasing inter-cell isolation resistance.
Although in the construction shown in FIG. 6, the cell isolation regions 230 and the cell regions 240 are at different levels, such level difference can be eliminated with ion implantation method. FIG. 7 is a sectional view showing a prior art device prepared by the ion implantation method. Ions are implanted into cell regions 240 to form N-type regions 360. After forming gate patterns 260, ions are further implanted to form N-type region 350 and 370. Isolating regions 230 between cell regions 240 are not implanted with ions. In the case of the ion implantation method too, heat treatment causes the resistance of the substrate at the cell isolating region to decrease. For this reason, it has been impossible to make the cell isolation regions small, making it difficult to integrate cells at high desities. Where insulative ions such as chromium are doped into the cell isolation region, for the purpose of preventing decrease in the cell isolation resistance, such insulative ions may be further added to compensate the degrees in the cell isolation resistance. To implant such insulative ions, a mask has been used. But this method disadvantageously requires preparation and use of a mask.